************************************** * * * Transgalactic * * Instruments * * * ************************************** * * * This is the Nukeman mainboard 2 ATA coolrunner. * It stands between the 68340 bus and the ATA interface. * * It is relied on the lc taking the pin (.p, .pin) signal as defauult * when mo signal modifier is specified. * * * * address space decoded as follows: * addresses as seen from the cpu (i.e. a7 is a7) * * 0 to 3f - slot 0 (cs0 and cs1 just follow a4 and a5) * 40 to 7f - slot 1 (FDD and CD, cs0 and cs1 same as above) * 80 to 8f - control register * c0 to cf - fake dma data register (asserts dack and ior/w of the channel * with enabled dma (dma0e and dma1e) ) * * name mainboard_2_ATA_interface_1.0. device cr64p100 * input macr ifeq \#-2 \0: pin \1,high oe 0 endc ifeq \#-3 \0: pin \1,\2 oe 0 endc endm * * Sysdata macro.Used below to define d0-15 * syntax: sysdata , * since a5 is input only, its .i output is used to control the OE * sysdata macr d\0 pin \1,high @setl currdd {\0+8!.$f} oe a5.i&as ifudf ctl\0 logic dd]currdd .p endc ifdef ctl\0 logic dd]currdd .p&!a7.p&!sysdack' #dd]currdd .p&a7.p&a6.p&!sysdack' #]ctl\0 &a7.p&!a6.p&!sysdack' #dd]currdd .p&sysdack endc endm * * * * Atadata macro.Used below to define dd0-15 * syntax: atadata , * a6' .i output is used for OE control (.p is a6, OE of a6 is 0) atadata macr dd\0 @setl currdd {\0+8!.$f} pin \1,high oe a6.i logic d]currdd .p endm * * define control bit macro * syntax: * ctl ,, ctl macr @setl \0 \1 @setl \0e \1.i ctl\2 equ \2 just to have ctl\1 defined @setl ctl\2 \1.i endm * * define control register bits - just local variables * * ctl dma0,qdrq,0 bit 0 - enable dma slot 0 ctl dma1,d1e,1 bit 1 - enable dma slot 1 ctl irq0,a4,2 bit 2 - enable irq from slot 0 ctl irq1,as,3 bit 3 - enable irq from slot 1 ctl qdma,sysdack,4 bit 4 - qdma DMA mode (drq=qdrq&drqX) ctl reset,reset,5 bit 5 - reset to (all) ATA devices ctl pdir,int0,6 bit 6 - padd direction ctl scsi,int1,7 bit 7 - enable SCSI dma ctl padd,padd,8 bit 8 - padd dack/iow until drq * * * drq0 used to initially reset the reset * * * * * signal definitions * * inputs from 68340 input clk0,87 just define main clock (68340 clkout) input a7,14 also used as IRQ enable bit input a6,12 input a5,42 input a4,41 * input sel,6,low select from main_pld input as,44,low input rw,45 input sysdack,9,low input scsidrq,90,high drq from NCR53CF96 chip (also qdrq gateable input berr,13,low berr of 68340 - qspan drives it * input qdrq,8,low drq from qspan * * retry detector retry cell d8,high oe 0 notclk clk0 logic as&berr&sysdack' #retry.i&!as' #retry.i&!sysdack&!sel * * * scsi dack also gated to accomodate retries etc. * scsidack pin 47,low oe 1 logic sysdack&]scsie &!]dma0e &!]dma1e ' #scsidack&retry.i * * irq * IRQ can be forced low by enabling both dma0 and dma1 for test * purposes during powerup initializations * irq pin 46,low oe 1 irq 4 used by ata only logic int0&]irq0e ' #int1&]irq1e ' #]dma0e &]dma1e * * * inputs from ATA * input drq0,65 drq from slot 0 (system hdd) input rdy0,71 rdy from slot 0 input int0,76 int from slot 0 * input drq1,98 drq from slot 1 input rdy1,89 rdy from slot 1 input int1,75 int from slot 1 * * drq0 cell used for powerup reset of the coolrunner drq0 clk as logic !a7#drq0.i just get set as soon as possible * * outputs to ATA * cs0 pin 80,high oe 1 logic sel&!a7.p&a4.p&!sysdack * cs1 pin 81,high oe 1 logic sel&!a7.p&a5.p&!sysdack * * rdy0.i used as delayed AS to delay iow * @setl dlydas rdy0.i rdy0 notclk clk0 logic as * * a7.i used to generate the padd ior/iow pulse delay * a7 notclk clk0 logic ior0' #iow0' #ior1' #iow1 * * ior0 pin 69,low oe 1 logic sel&!a7&!a6&rw&as&!sysdack&]dlydas ' #]dma0e &sel&a7&a6&rw&as' #sysdack&]dma0e &!rw&as' #dack0&]padde &!a7.i&]pdire ' #ior0&retry.i * iow0 pin 67,low oe 1 logic sel&!a7&!a6&!rw&as&]dlydas &!sysdack' #]dma0e &sel&a7&a6&!rw&as&]dlydas ' #sysdack&]dma0e &rw&as&!]qdmae ' #dack0&]padde &!a7.i&!]pdire ' #iow0&retry.i * ior1 pin 68,low oe 1 logic sel&!a7&a6&rw&as&!sysdack&]dlydas ' #]dma1e &sel&a7&a6&rw&as' #sysdack&]dma1e &!rw&as' #dack1&]padde &!a7.i&]pdire * iow1 pin 1,low oe 1 logic sel&!a7&a6&!rw&as&]dlydas &!sysdack' #]dma1e &sel&a7&a6&!rw&as&]dlydas ' #sysdack&]dma1e &rw&as&!]qdmae ' #dack1&]padde &!a7.i&!]pdire * dack0 pin 79,low oe 1 logic sysdack&]dma0e &!]dma1e &!]scsie &as&!rw' #sysdack&]dma0e &!]dma1e &!]scsie &as&rw&!]qdmae ' #]dma0e &sel&a7&a6&as' #]dma0e &]padde &drq0&!sel' #]dma0e &]padde &dack0&ior0' #]dma0e &]padde &dack0&iow0' #dack0&ior0' #dack0&iow0 * dack1 pin 48,low oe 1 logic sysdack&]dma1e &!]dma0e &!]scsie &as&!rw' #sysdack&]dma1e &!]dma0e &!]scsie &as&rw&!]qdmae ' #]dma1e &sel&a7&a6&as' #]dma1e &]padde &drq1' #]dma1e &]padde &dack1&ior1' #]dma1e &]padde &dack1&iow1' #dack1&ior1' #dack1&iow1 * drq pin 10,low *** notoe !]dma0e &!]dma1e &!]scsie oe 1 logic drq0&]dma0e &!]dma1e &!]scsie &!]qdmae ' #drq0&]dma0e &!]dma1e &!]scsie &]qdmae &qdrq' #drq1&]dma1e &!]dma0e &!]scsie &!]qdmae ' #drq1&]dma1e &!]dma0e &!]scsie &]qdmae &qdrq' #scsidrq&!]dma0e &!]dma1e &!]qdmae &]scsie ' #scsidrq&!]dma0e &!]dma1e &]qdmae &]scsie &qdrq * * system da1 (dsa1) USES RW.i for OE control * da1 pin 2,low still to be routed... oe rw.i&!sysdack logic iow0&rdy0&as&!]qdmae ' #a7.i&rdy0&as&]qdmae ' #ior0&rdy0&as' #iow1&rdy1&as' #ior1&rdy1&as' #sel&a7&!a6&as' #da1.i&as * * rw notclk clk0 preset as&sel&!sysdack logic as&sel&!sysdack * * control register bits * * ]dma0 notclk clk0 clr !drq0.i logic d0.p&sel&as&a7&!a6&!rw' #]dma0 .i&!as' #]dma0 .i&rw' #]dma0 .i&!sel' #]dma0 .i&!a7' #]dma0 .i&a6 * ]dma1 cell c15,high notclk sel&as&a7&!a6&!rw clr !drq0.i logic d1.p * ]irq0 notclk sel&as&a7&!a6&!rw clr !drq0.i logic d2.p ]irq1 notclk sel&as&a7&!a6&!rw preset !drq0.i logic d3.p ]qdma notclk sel&as&a7&!a6&!rw preset !drq0.i logic d4.p * reset pin 92,low preset !drq0.i oe 1 notclk sel&as&a7&!a6&!rw logic d5.p * * * ]scsi notclk clk0 clr !drq0.i logic d7.p&sel&as&a7&!a6&!rw' #]scsi .i&!as' #]scsi .i&rw' #]scsi .i&!sel' #]scsi .i&!a7' #]scsi .i&a6 * ]padd cell b15,high notclk sel&as&a7&!a6&!rw clr !drq0.i logic d8.p * ]pdir notclk clk0 clr !drq0.i logic d6.p&sel&as&a7&!a6&!rw' #]pdir .i&!as' #]pdir .i&rw' #]pdir .i&!sel' #]pdir .i&!a7' #]pdir .i&a6 * * * a5's .i output controls the tsc of sysdata (AS gated in the OE terms) * a5 logic sel&rw&!sysdack' #sysdack&!rw&!]scsie * *** sysdata 15,37 68340 d15 d15 pin 37,high oe a5.i&as logic dd7.p&!a7.p&!sysdack' #dd7.p&a7.p&a6.p&!sysdack' #dd7.p&sysdack' #drq0&]dma0e &a7.p&!a6.p&!sysdack' #drq1&]dma1e &a7.p&!a6.p&!sysdack * sysdata 14,21 sysdata 13,23 sysdata 12,19 sysdata 11,20 sysdata 10,16 sysdata 9,17 sysdata 8,32 sysdata 7,40 sysdata 6,25 sysdata 5,30 sysdata 4,29 sysdata 3,31 sysdata 2,33 sysdata 1,35 sysdata 0,36 * * output controls the tsc of ATA data * a6 logic sel&as&!rw&!sysdack' #sysdack&as&rw * atadata 15,64 atadata 14,61 atadata 13,58 atadata 12,56 atadata 11,52 atadata 10,96 atadata 9,93 atadata 8,84 atadata 7,83 atadata 6,85 atadata 5,94 atadata 4,97 atadata 3,54 atadata 2,57 atadata 1,60 atadata 0,63 * * * END *